SBIR-STTR Award

Maintaining minimal real-time latency for the acquisition and distribution of the significant data volume required by pulse-to-pulse feedback loops in a high rate linear collider presents serious challenges. The problem is made more difficult when long distances make maintaining complicated remote computers impractical and increase signal propagation delays for non-local communications. This project will utilize intelligent input-output (I/O) boards for personal computers in a central computing room communicating via single mode fiber optics with highly reliable remote serial I/O ports with embedded user code triggered by beam timing signals. The system will be designed for minimum remote hardware/software complexity and optimized for minimum real-time latency at every point. Phase I will identify and/or design the necessary fiber optic link protocols and the processor/real-time executive firmware combination required for the remote I/O ports. Preliminary design of the personal computer I/O board and a remote I/O port suitable for use in a test bed at the Stanford Linear Collider will be performed.

Commercial Applications and Other Benefits as described by the awardee:
The system is designed to increase the reliability, improve the maintainability, and increase the software development efficiency of the next generation electron-positron linear collider.

In a high rate linear collider, it is difficult to maintain minimal real-time latency for the acquisition and distribution of the significant data volume required by pulse-to-pulse feedback loops. The problem is made more difficult when long distances complicate remote computer maintenance and increase signal propagation delays. This project will utilize intelligent I/O boards for personal computers in a central computing room communicating with highly reliable remote serial I/O ports containing embedded user code. Communications links will be provided by noise-tolerant protocols on single-mode, fiber optic cables. Phase I identified the link hardware and designed the noise-tolerant protocols. The processor environment in the remote I/O port was selected and a preliminary design of the link interface hardware was performed. A remote I/O port for possible use in a test bed at the Stanford Linear Collider was also designed. Phase II will develop a working prototype containing the remote I/O port, a ten kilometer noise-tolerant link to a central computer, and a noise-tolerant link to a prototype device controller. In addition, software will be written to help validate the remote I/O port concept.

Commercial Applications and Other Benefits as described by the awardee:
The system should increase reliability, improve maintainability, and increase software development efficiency for the next generation electron-positron linear collider.