SBIR-STTR Award

A custom high desity VLSI circuit for time projection chamber readout
Award last edited on: 2/20/2002

Sponsored Program
SBIR
Awarding Agency
DOE
Total Award Amount
$50,000
Award Phase
1
Solicitation Topic Code
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Principal Investigator
Raymond S Larsen

Company Information

Analytek Limited

845 Oak Grove Avenue Suite 100
Menlo Park, CA 94086
   N/A
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Location: Single
Congr. District: 17
County: Santa Clara

Phase I

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase I year
1991
Phase I Amount
$50,000
The new generation of Time Projection Chambers (TPCs), such as the Relativistic Heavy Ion Collider at Brookhaven National Laboratory, produce large amounts of data on every event. As a result, a new generation of TPC electronics, employing a frontend data compaction scheme, is required to extract the interesting data from the enormous total data set. Two approaches are being studied in Phase I. In both cases, signal capture utilizes an analog sampling array, which is a technology developed especially for physics laboratory use, and is now the basis of a unique line of commercial measuring instruments. The first variation studied is the detection of valid data with a front-end discriminator on every channel; the discriminator, working in conjunction with a timing clock, records the time at which the event begins, then takes a specified number of samples, which are stored in an analog memory. The time values are stored separately. After the drift period is over, the analog samples are read out and converted in an analog-to-digital convertor; the amplitude values and time stamp are stored in a local memory for further collection and processing. In the second approach, the entire drift period is digitized, and the samples of interest are detected on readout. At this time, signals below threshold are discarded, and the valid data along with the calculated time value(s) are stored as before. In both approaches, only the data of interest enter the next stage of processing.Anticipated Results/Potential Commercial Applications as described by the awardee:This project's main goals are to assess the tradeoffs of the two architectures; the requirements for peripheral circuits, or additional custom chips, for preamplification, correction, readout, and processing; the achievable channel density; the evaluation of best silicon technology; achievable channel density versus power consumption; and the projected cost of a complete channel. Potential commercial applications, with chip features that address these applications, are anticipated.

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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Phase II Amount
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