SBIR-STTR Award

Development of a Low Cost Clustered VAXBI FASTBUS Interface
Award last edited on: 4/10/02

Sponsored Program
SBIR
Awarding Agency
DOE
Total Award Amount
$533,452
Award Phase
2
Solicitation Topic Code
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Principal Investigator
Eric J Siskind

Company Information

NYCB Real-Time Computing Inc

18 Meudon Drive
Latttingtown, NY 11560
   (516) 759-0707
   nycbrealtime@verizon.net
   N/A
Location: Single
Congr. District: 03
County: Nassau

Phase I

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase I year
1989
Phase I Amount
$45,360
A low cost clustered intelligent list-processing interface between the VAXBI and FASTBUS will be developed. The VAXBI is the 13.3 megabyte/sec backplane interconnect featured in VAX 6210 through 6240, 6310 through 6360, 8200, 8250, 8300, 8350, 8500, 8530, 8550, 8700, 8800, and 8810 through 8840 systems, as well as configurations constructed by clustering these systems and other future VAX systems. The intent is to provide a modem interface between a variety of VAX configurations and FASTBUS, while featuring (1) the hardware reliability, maintainability, and cost effectiveness of modern application specific, very large scale integrated (VLSI) circuitry and (2) the simplicity of design associated with a layered software structure designed to support intelligent storage controllers located in a networked clustered environment. The hardware will consist of several elements: a microcoded VAXBI I/O processor board manufactured by Digital Equipment Corporation; a second VAXBI board containing data buffers and one end of a high speed data link, probably implemented with 100 megabit/sec optical fiber cabling; a FASTBUS auxiliary back- plane card containing the other end of the link, and a single width FASTBUS module containing a buffered high speed unintelligent FASTBUS master and slave interface. Besides the firmware for the I/O processor, the software will consist of a VAX/VMS port driver, a VAX/VMS class driver, and a remote I/O server tightly coupled with the kernel of the VAX/VMS executive. This last element will permit a FASTBUS user who is utilizing a class driver in one VAX to access a port driver and hardware interface resident in another VAX through any intervening clustering medium, e.g., the 10 megabit/sec Ethernet, the 70 megabit/sec Cluster Interconnect (CI), or any future such medium.Anticipated Results/Potential Commercial Apl)lications as described by the awardee:A direct means of connecting the FASTBUS to the latest generations of VAX processors will facilitate the use of these and future processors in experiments in elementary particle physics and other disciplines requiring FASTBUS use. Potential applications exist in upgrades to existing large detectors at colliding beam facilities and in smaller fixed target experiments that may be constructed before the next generation of colliders becomes operational, as well as lower energy accelerators being constructed for nuclear physics experiments.

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
1990
Phase II Amount
$488,092
A low cost clustered intelligent list-processing interface between the VAXBI and IEEE-960 FASTBUS will be developed. The VAXBI is a proprietary backplane found in VAX computers. Interface hardware consists of a front end processor card and communication link located in a VAXBI card cage plus a FASTBUS card containing the other end of the link and an unintelligent FASTBUS interface implemented in programmable very large scale integrated logic. Firmware consists of microcode for the VAXBI processor card plus the configuration data for programmable logic. Software includes class and port drivers for VAX/VMS plus a remote input/output server which permits transparent class driver access from other VAX processors attached to the same cluster medium. In Phase I the hardware architecture was fixed and a VAXBI license was obtained. The formats of messages passed between the class driver and the front end processor microcode were also determined. In Phase II, a complete prototype system, including hardware, firmware, and software, will be designed, constructed, and debugged.Anticipated Results/Potential Commercial Appliations as described by the awardee:A direct means of connecting the FASTBUS to the latest generation of VAX processors will allow these and future processors to be used in high energy physics and other disciplines requiring FASTBUS use. Potential applications exist in upgrades to existing large detectors at colliding beam facilities and in smaller fixed target experiments that may be constructed before the next generation of colliders becomes operational, as well as in lower energy accelerators being constructed for nuclear physics experiments.