Increasingly large and densely packed sensor arrays for calorimeters, Cerenkov ring imaging, and time projection chamber systems are placing more stringent demands on front-end electronics. The noise performance and dynamic range requirements of these preamplifiers are very stringent and to some degree must be tailored to the application. Recent experience with large scale hybridization of such preamplifiers has shown the clear limitations of the hybrid approach in size, external circuit complexity, and cost. This project will study the feasibility of developing a major building block or blocks for a multichannel preamplifier using with current very large scale integration (VLSI) technology. Special problems include the coupling of an extremely low integration capacitance and high transconductance field-effect transistor front end to a bipolar or metal oxide semiconductor main section, plus an optional buffer section capable of driving a relatively high capacitive load, such as is typically found in back-end electronics for waveform sampling. A major hurdle to the further integration of front-end data acquisition electronics is the development of high density preamplifiers and associated calibration and shaping electronics. Recent advances in sampling and multiplexing electronics cannot be fully utilized without similar improvements in preamplifier building blocks. The objective is to design major VLSI blocks using the latest available chip technologies that will combine traditionally discrete preamplifier and support circuit designs onto a common building block. It is important to emphasize the requirement for a systems approach to the problem, since the support circuits can introduce considerable systems complexity if they are not also included in the design.Anticipated Results/Potential Commercial Applications as described by the awardee: The goal is to achieve at least four and preferably eight channels on a single chip, with crosstalk isolation of less than 60 dB, input noise of less than 1000 electrons, output voltage of 2 V full scale, bandwidth of approximately 20 MHz, controllable pole-zero shaping, and a dynamic range of 16 bits. The unit described is essential to further progress and packaging density improvement in sampled data systems since the current art is limited to single channel monolithic and hybrid designs for this type of amplifier. An integrated building block will serve a variety of applications in physics. Commercial applications are primarily in the area of imaging for medical and sonar scanning arrays, in which very low signals must be detected and processed accurately.Topic 16: High Energy Physics Data Processing and Detector Instrumentation
