SBIR-STTR Award

Automatic FPGA and IC Run-time Monitor (AFIRM)
Award last edited on: 3/29/2023

Sponsored Program
SBIR
Awarding Agency
DOD : DMEA
Total Award Amount
$167,382
Award Phase
1
Solicitation Topic Code
DMEA221-001
Principal Investigator
Christopher Diltz

Company Information

EDAptive Computing Inc

1245-G Lyons Road
Dayton, OH 45458
   (937) 433-0477
   info@edaptive.com
   www.edaptive.com
Location: Multiple
Congr. District: 10
County: Montgomery

Phase I

Contract Number: HQ072722P0020
Start Date: 7/22/2022    Completed: 2/1/2023
Phase I year
2022
Phase I Amount
$167,382
Develop a library of practical synthesizable register transfer logic (RTL) assertions (System Verilog is highly preferred), investigate limitations of synthesizable assertions in both integrated circuit (IC) and field programmable gate array (FPGA) design and design verification flows using already existing EDA platforms, and develop a methodology for synthesizable RTL assertions and error reporting. Identify robust test vehicles and implement synthesizable RTL assertions in both an FPGA and an IC.

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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Phase II Amount
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