SBIR-STTR Award

The Tela Canvas 1D gridded design style will be applied to logic standard cell and SRAM designs. EDA tools to support the design will be developed, and representative layouts will be created using these tools.

Keywords:
1d Gridded Design, Regular Design, Maskless Lithography

Through this DARPA SBIR Phase II program, we plan to extend our previous point-solution demonstration (DARPA seedlings) to include logic, SRAM, and IO's and deliver the EDA tool to enable DoD ASICs to take full advantage of our commercial experience. Our Phase I effort to date has shown a path to the EDA tools and design infrastructure needed to meet the goals outlined above. The software engineering tool “Gridded Design Assistant” has been demonstrated for a representative set of ten standard cells. We are well along in the second part of the Phase I effort, i.e. demonstrating an SRAM bit-cell and peripheral circuitry compatible with the regular layout style used for the standard cells.

Keywords:
GRATE, 1D design style, Gridded Design Assistant, regular layout style