SBIR-STTR Award

Design and Fabrication Techniques for 3-Dimensional Integrated Circuits
Award last edited on: 6/28/2010

Sponsored Program
SBIR
Awarding Agency
DOD : DARPA
Total Award Amount
$98,955
Award Phase
1
Solicitation Topic Code
SB091-008
Principal Investigator
Robert Patti

Company Information

Tezzaron Semiconductor Corporation

1415 Bond Street Suite 111
Naperville, IL 60563
   (630) 505-0404
   info@tezzaron.com
   www.tezzaron.com
Location: Multiple
Congr. District: 06
County: DuPage

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2010
Phase I Amount
$98,955
Tezzaron proposes to use and extend its 3D wafer stacking technology to produce a 8Gb DRAM. The device will be made from 8 layers of memory and a single logic control layer, providing density far beyond the capability of current commercial technology. A device of this density can offer significant improvements in system power, size, weight and performance. The major unknown in creating a device like this, are the issues that may arise when 3D integration is practiced beyond Tezzaron current devices of 3 or 4 tiers. In Phase I "dummy" wafers will be stacked to determine the feasibility of the planned 9 layer device to be fabricated as part of Phase II.

Keywords:
3d-Ic,Memory,Stacked,Wafer To Wafer,High Density,Tsv,Thermal Diffusion,Bonding

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
----
Phase II Amount
----