This proposal demonstrates the feasibility of top-down, VHDL-based verification of gigascale, integrated, mixed-signal system-on-a-chip for military applications. Building on FTL Systems' unique parallel-compile, parallel-execute HDL compiler/simulator, this effort introduces novel analog solver, iterative optimization, parallel processing and hardware acceleration technology. These novel technologies enable the gigascale, mixed-signal designer to optimize design parameters such as integration density, cross-talk, interconnect latency, power/thermal management and fault-tolerance using VHDL, VHDL-AMS, and VHDL-RF/MW with a 100x to 1000x verification time reduction. Since verification accounts for more than half the design cycle time, a 10x to 100x reduction in design cycle time results. The anticipated Phase II design target uses 3-D die stacking technology to shrink an avionics processor and associated I/O processing complex by more than 10x with a first pass correct-functionality objective. Ability to accurately and rapidly verify giga-scale, mixed-signal designs conveys key advantages for integrated avionic processor complexes (such as those developed for the JSF), commercial wireless communication devices (such as those developed by the Bluetooth Consortium) and for integrated electronic and photonic systems (such as medical image processing systems). These advantages include denser packaging, lighter weight, lower-power consumption, higher reliability, lower design cost and lower production costs in the context of gigascale, high-frequency, mixed-signal systems. FTL Systems has the commercial relationships to rapidly impact all three of these application areas with commercial products.
