SBIR-STTR Award

Circuit simulation is a critical bottleneck in design of complex VLSI chips. Even though clock speed and processing power of general purpose workstations are improving constantly, increases in size and complexity of VLSI chips indicates that this problem will only get worse. In the past, this problem has been addressed using special purpose hardware; example systems include the IBM Yorktown Simulation enginer, the Zycad XP simulation booster and FPGA based circuit emulators. These approaches require special purpose hardware and are expensive; they are also not inherently scalable. Perhaps the most promising approach is the use of general purpose, scalable, massively-parallel technology developed under the HPCC initiative for parallel execution of circuit simulation programs. Depending on circuit parameters, it is possible to get significant speedups from relatively inexpensive parallel architectures (e.g. multi-systems like the Thinking Machine CM5 and the Intel Paragon. The result of Phase I will be a detailed report outlining the technical methodology to be used to develop a next-generation parallel circuit simulator for general purpose parallel processing computers as well as detailing a productization strategy that will guarantee easy adoption within the EDA industry. ANTICIPATED

Benefits:
There is a great need within the EDA industry for new parallel processing simulation technology for general purpose parallel processing hardware. The proposed work will lead directly to a commercial simulation product.