SBIR-STTR Award

Dual Chipset ASIC and FPGA Approach for a Low Cost , Flexible, LPD Radio, Applique
Award last edited on: 9/6/22

Sponsored Program
SBIR
Awarding Agency
DOD : Army
Total Award Amount
$199,952
Award Phase
1
Solicitation Topic Code
A214-004
Principal Investigator
John D Terry

Company Information

Terry Consultants Inc (AKA: TCI)

3033 Wilson Boulevard Suite 700
Arlington, VA 22201
   (703) 349-5641
   info@terryconsult.com
   www.terryconsult.com
Location: Single
Congr. District: 08
County: Arlington

Phase I

Contract Number: W56KGU-21-C-0046
Start Date: 9/13/21    Completed: 12/15/21
Phase I year
2021
Phase I Amount
$199,952
TCI seeks to develop and produce an innovative, low-cost dual chipset ASIC/FPGA SWAP optimized communications platform that operates as Soldier borne electromagnetic warfare protection (EMWP) module. The comparative benefits of FPGA design versus ASIC designs are well-established in the semiconductor and manufacturer design industries. The pros for FPGA designs are extremely flexible platforms for designs that are software re-configurable and typically paired with high performance processor, industry standard I/O, and RAM. The cons for FPGA include high power consumption and high unit cost per design gate compared to ASIC designs. The pros for. ASIC designs are extreme efficiency, full customization of gates toward design objective which leas to superior power consumption, reduced area for the design and typically operational clock speed. Lastly, a couple orders of magnitude reduction in unit cost per design gate. The cons for ASIC Include no modifications to the design without spinning another chip, long lead times for tape-out for chip fabrication, In proposed design, we examine a single board design containing a high performance FPGA and custom ASIC EMWP Signal Encapsulation chip. Incorporating the industry-leading interface standard AMBA AHB bus interface will enable high speed interconnection between the FPGA subsystem and ASIC as well as components. The ASIC EMWP is capable of direct sequence spreading (DSS) of binary data (0,1) or external digital IQ samples. The FPGA will be used to produce on-board digital IQ sample for lower rate source as a legacy radio, audio codec, and compressed video codec. The ASIC will generate a low probability of detection (LPD) payload by DSS the digital IQ samples or bits with a high speed featureless waveform running at either 20 MHz, 40 MHz or 80 MHz, depending on the register configuration. The entire radio frame including training fields will be resilient to interference, electronic attack, and afforded a measure of low probability of intercept (LPI) along with LPD. This baseband LPB modem design will be paired with off-the-shelf wideband commercial transceivers and high-speed data converters (e.g. A/D and D/A). onto a single multi-layer board design. Custom lightweight ruggedized enclosures will enable the design to support a multitude of dual use applications such as expeditionary communications in the public safety sector, tactical small-medium size teams in military at the tactical edge, and large scale low powered device for Edge IoT applications.

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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Phase II Amount
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