Tactical Computing Laboratories (TCL) has considerable experience designing processors utilizing both RISC-V as well as completely custom ISAs. Our architecture will be designed and simulated through modifications to our existing, powerful, hardware generation environment, OpenSoC System Architect. We propose a complete co-design environment that brings together automatic generation of not only hardware, but also compilers and cycle accurate simulators that can be run in seconds to minutes creating a tight, powerful co-design loop for rapid iteration from hardware specification to software optimization. We will combine this auto-generation path with development of a full system, cycle approximate software simulation environment. Our co-design environment will be utilized to create a powerful RISC-V based DSP accelerator that combines multiple architectural features focused on maximizing throughput, Instruction Level Parallelism (ILP), pipeline efficiency, and latency hiding techniques all while preserving general purpose programming performance. Our proposed architecture will have full support for RV64G while simultaneously delivering best-in-class performance on critical DSP kernels, including: matrix-matrix multiplication, convolution, FIR Hilbert transforms and FFTs. Our proposed DSP instruction extensions allow RISC-V based DSP accelerators to move beyond fixed-point and integer data types and operate efficiently on single and double precision floating point values. We also propose a novel set of data movement operands that allow powerful gathering of non-contiguous operands to to maximize utilization of packed SIMD pipelines. While focused on performance, our proposed ISA extensions will be capable of effectively meeting the needs and requirements of the full range of users - from embedded to High Performance Computing (HPC). As RISC-V is a community driven organization, by targeting the broadest possible set of workloads is the most efficient path to adoption.
