The Ampex design for LTR-RIP has shifted from a conduction-cooled avionics-type system to a ruggedized standard rack system, with enhanced forced-air cooling. The results of Phase I of this SBIR have led to the requirements of of Phase II which can be broken down into several inter-related goals. FPGA Aurora II Interface: To interface correctly with the Advanced Data RF-Receiver (ADR), an interface that implements the Xilinx Aurora II protocol is required. This will be implemented in a commercial FPGA card and this card provides a QSFP-DD interface and a PCI Express connection. The Xilinx FPGA is a Xilinx Virtex UltraScale Plus VU33P-2E device, and the device as a whole is specifically designed to be able to serve as a 100 gigabit Ethernet accelerator. Packetization: The data stream from the ADR loses its structure once it leaves the QSFP28 interface on the ADR. This absence of structure presents few, if any, problems while monitoring the data in real time, but the lack of metadata, both synchronous and asynchronous, poses challenges when processing stored data. Ampex plans to solve this problem by using VITA 49 radio transport to encapsulate a group of I/Q data samples between a header and a footer, together with a high-precision timestamp and a mechanism to allow for context packets to coexist with the data packets in the same stream. Once packetized with timestamps and context metadata, the signal stream can be split into coherent parts, each with enough metadata to be able to process the fragment. The objective in the LTR-RIP is to packetize the data stream in the FPGA as it is received from the Aurora II section, but before sending it to host memory. To complement this task, the ACCE framework will insert asynchronous metadata alongside the bulk ADR stream. By packetizing the data, not only is the utility of the recording enhanced, but the potential future enhancements in the area of parallelized tagging and annotation are facilitated. Core System Packaging: Ampex will design and produce an enclosure that provides airflow and heat dissipation to the components that need it, that secures the subcomponents and cable assembly against appropriate levels of shock and vibration, and uses connectors suitable for a system intended to be transportable. Storage Packaging and Enclosure: As with the system enclosure, the high-speed storage array needs to be packaged so as to efficiently cool the devices; the high-capacity, high-performance NVME SSDs typically have mechanisms to limit their performance when the temperatures of the individual flash cells reach a preset level, so suitable cooling is essential. In addition, the CONOPS of the LTR-RIP and possible future applications indicate a removable storage tray would be highly beneficial to allow quick removal and securing of sensitive data as well as for further analysis in a data center environment. The removable storage tray will be designed to hold 12 SSD's allowing up to 184TB of data storage.
