SBIR-STTR Award

Low Power Monolayer MoS2 Transistors for RF Applications
Award last edited on: 1/9/2015

Sponsored Program
STTR
Awarding Agency
DOD : Army
Total Award Amount
$650,008
Award Phase
2
Solicitation Topic Code
A14A-T008
Principal Investigator
Rajesh Rao

Company Information

Applied Novel Devices (AKA: A.N.D. Inc)

15844 Garrison Circle
Austin, TX 78717
   (512) 775-7991
   N/A
   www.appliednoveldevices.com

Research Institution

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Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2014
Phase I Amount
$150,000
The objective of this proposal is to demonstrate the feasibility of producing large area, single crystal monolayer Molybdenum disulfide (MoS2) for high frequency applications. In order to be able to achieve this aim, it is necessary to work on three main components: (a) the channel material itself, (b) the gate dielectric and (c) the drain/ source contacts to the channel material. This work proposes to use optimization of chemical vapor deposition (CVD) growth parameters for obtaining large domain single layer MoS2 on device quality substrates, use of hexagonal Boron Nitride (h-BN) as a dielectric and its growth directly on Si-SiO2 to remove the need for any transfer before MoS2 growth and the use of highly conductive ?defects? on the MoS2 surface to enhance charge injection in the metal- semiconductor interface.

Keywords:
Mos2, Cvd, Monolayer, Low Power Rf, 2-Dimensional, Fet

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
2015
Phase II Amount
$500,008
In Phase II we propose to optimize wafer scale MoS2 deposition process to fabricate uniform large area monolayer and multi-layer MoS2 films and analyze the defects on these films. Monolayer regions that can result in device periphery larger than 50m will be targeted. Further, the charge transfer doping process using TiOx will be optimized for MoS2 multi-layer and RF transistors will be fabrication on these multilayers. The device structure (geometry, length of underlap region, choice of gate dielectric, gate and contact materials) will be optimized to meet DC and RF performance targets of this solicitation. The transistors will be targeted to show an RF performance of fmax > 20GHz