This project will extend the performance and capabilities of an existing and proven Silicon-on-Insulator (SOI) high temperature gate drive integrated circuit developed by the University of Tennessee (UT) to meet the Armys requirements for a high performance SiC Gate Drive. GPE and UT will develop circuits that add high temperature galvanic isolation, high current SiC buffer drivers, and inherently safe operation with normally-on devices. Electrical and Thermal analysis will be performed at the prescribed operating temperatures and frequencies for all three types of SiC power switches. The deliverable for Phase I will be a project report with simulation results and recommendations for Phase II. The objective for the Phase I Option is to prepare for the Prototype fabrication in Phase II. GPE will conduct a conceptual packaging study to determine the best electrical layout for high frequency and the best thermal layout for reduction of device temperatures and stress reduction. Currently there are no commercially available low voltage SiC devices for a small footprint buffer circuit so another task will be to optimize the SiC buffer for low voltage operation.
Keywords: Silicon Carbide, Gate Drive,High Temperature, High Frequency, Galvanically Isolated
