SBIR-STTR Award

Today’s field-programmable gate array (FPGA) devices are expensive in size, power, performance, scalability and flexibility. The fundamental problem in these devices is the use of 2D-mesh interconnect architecture: it occupies large area, has long latency, consumes lots of power, and is not scalable. Interconnect takes more than 75% of the FPGA chip area. A large number of inactive transistors also produces significant leakage power (about 50% of the total FPGA power). Previous attempts in building hierarchical networks failed due to problems with routing congestion. HierLogix offers to develop a revolutionary FPGA technology consisting of FPGA hardware and supporting mapping tools. The proposed work is a radical departure from 2D-mesh design, which for N logic blocks has complexity O(N2), incomplete and heuristic routing. The proposed technology has only O(N·log2N) complexity, complete and fully deterministic routing. It also has greatly reduced routing congestion compared to prior attempts in hierarchical networks, which makes the approach practical. We will specify architecture of FPGA and develop mapping tools to demonstrate FPGA technology that is 10x more energy-efficient than existing FPGAs.

Keywords:
Fpga, Hierarchical Interconnect, High-Performance, Low-Power, Programming Tools