SBIR-STTR Award

This proposal presents two approaches to increase the DDS analog output bandwidth beyond 3 GHz to extend the required jamming signal bandwidth for modern EW applications. As the sole supplier of > 3 GHz DDS and other DAC-related high speed mixed signal products in the worldwide open market, the proposed approaches are based on Euvis’ existing 3.2 GHz DDS products to minimize risks. The prime approach we propose to improve the speed of the DDS is the ping-pong architecture, where parallel implementation of DDS functions allows faster processing with little demand for increased transistor speed. The second approach is to utilize the 2nd and the 3rd Nyquist band with Euvis patented Return-to-Zero or Complementary Interpolation DACs. The module to be proposed includes the developed monolithic single chip DDS integrated on PCB with FPGA as the control, command and self testing. The module can be as small as 3” x 3” for a single channel which will have the operating characteristics of low cost, sub-microsecond response time, phase coherence, low phase noise and spurious content, high reliability, small size, power and weight.

Keywords:
Dds, Dac, Drfm, Ew, Jammers, Mobile Jammers, Radio Frequency, Fast Tuning, Radar, Fpga