SBIR-STTR Award

Stream processors can provide 100s of GOPS of performance at low power levels with full programmability from high-level programming languages. SPI proposes to evaluate the applicability of these stream processors to remote surveillance systems where tens to hundreds of GOPS of performance and interfacing to a variety of sensors is required. As part of this evaluation, algorithm mapping and hardware demonstration for video and audio sensor filtering, processing, and compression is proposed

Stream Processors (SPs) form a new class of image processors that offer performance scalable to Teraops, have efficiency comparable to ASICs, and are completely programmable from high-level languages. SP technology was developed over 8 years of DARPA-funded research in Stanford University that resulted in a working prototype IC, 3rd-generation software tools and working application software on an engineering board. Phase I of this SBIR evaluated the use of SPs for multiple concurrent DSP tasks such as audio/video processing in a remote sensor. The broad conclusions are that SPs provide excellent performance, efficiency and programmability for such tasks, can support multiple applications running currently, have excellent IO capability, and with a development platform that includes a modular software framework, SPs can benefit a wide range of products. While SPI is commercializing this technology by building SP ICs and focused reference designs for specific products within its target markets, Phase II proposes to build such a development platform to broaden the usability of these SP ICs, especially to benefit military systems with multiple video and other demanding signal processing tasks such as multi-mode remote sensing applications.

Keywords:
Stream Processors, High-Performance Dsp, Development Platform, Parallel Processing, Software Framework, Signal Processing, Video Processing