The performance of devices and integrated circuits using selectively doped heterostructure transistors (sdht) has increased dramatically in the past years. A large part of that performance improvement is due to the reduced feature size of the gate electrode. Record switching times (6 ps) have been achieved using gate lengths of 0.3 micrometers (um). Shorter gate lengths potentially will have even shorter switching times with novel effects such as velocity overshoot expected. Gain electronics corporation (gain) proposes to lay the foundation for processes ultimately reaching minimum dimensions of less tha 0.1 um. In phase i of this long term project we intend to develop test patterns for the investigation of sdht device scaling. Submicron patterns will be exposed by a direct-write e-beam system and methods of pattern transfer (wet chemical etch, reactive ion etch, ion milling) will be evaluated for accuracy and precision in transfering the pattern from resist to the wafer and for capability of maintaining high aspect ratios of the etch. At the end of the phase i period, gain will be ready to apply relevant pattern transfer methods to the ultra-submicron device applications of sdht devices and circuits.
