SBIR-STTR Award

This proposal describes a 3 mhz to 300 mhz jamming system. It will have the capability of changing bandwidth and frequency in milliseconds. These changes will be initiated by digital input. The system output level will be kept the same independent of bandwidth. Specifications include bandwidth 2 mhz to 64 mhz in one mhz steps. Output 1 watt - 10 watt range. The end product of this effort will be a working breadboard system and a final report describing the system and its performance.

The phase II objective is to build a frequency and bandwidth agile noise jammer with a frequency range of 3mhz to 300mhz adjustable in 1mhz steps and bandwidth of 2mhz to 64mhz adjustable in 1mhz steps. Program objectives are to achieve the following improvements over the phase I breadboard: 1. Reduction of volume mass and power consumption. 2. Improve performance-power output, recombination speed, and spurious control. 3. Cost effective design suitable for moderate quantity production. 4. A dedicated logic board which permits direct input of frequency and bandwidth without the aid of an external program. 5. An ieee488 bus interface which responds to a protocol friendly with existing associated equipments. 6. Separate or replaceable power supply module. 7. Rugged construction with attention given to reliability and maintainability.