ENGIN-IC, Inc. proposes a Phase I study to refine an innovative wafer scale phased array antenna design to support the requirement for V-band Transmit, SATCOM downlinks. Specific focus will be on key risks. These include, but are not limited to thermal management, at all levels of the system from MMIC channel to satellite radiators, MMIC sizing and layout, V-band RF transitions, and antenna design. Given the constraint of maximum element to element spacing is governed by fundamental laws of physics, the phased array antenna will require wafer scale packaging. By utilizing innovative chip-on-chip and chip-on-substrate technology, the ENGIN-IC team has developed an approach to achieving a highly integrated, reliable array for space applications. The output of the Phase I study will be an array concept and demonstrator concept that is scalable and can be used across multiple platforms.
