SBIR-STTR Award

Reliable Logic Compatible Embedded Flash for Cost-Effective Secure SoC
Award last edited on: 1/13/20

Sponsored Program
SBIR
Awarding Agency
DOD : AF
Total Award Amount
$49,785
Award Phase
1
Solicitation Topic Code
AF191-005
Principal Investigator
Seung-Hwan Song

Company Information

Anaflash Inc

440 North Wolfe Road
Sunnyvale, CA 94085
   (408) 499-1853
   info@anaflash.com
   www.anaflash.com
Location: Multiple
Congr. District: 17
County: Santa Clara

Phase I

Contract Number: FA8751-19-P-A062
Start Date: 3/6/19    Completed: 6/4/19
Phase I year
2019
Phase I Amount
$49,785
Logic compatible embedded Flash (eFlash) is a cost-effective on-die non-volatile memory; however, it is not readily available in an advanced logic process due to limited retention of the memory cell and the reliability challenge of high voltage circuits. Our circuit design solutions uniquely address these issues and have been proven in multiple planar logic technologies. Throughout this project, we propose to develop a reliable logic compatible eFlash IP without any process overhead beyond baseline CMOS process.Compared to other logic compatible eFlash, our unique cell architecture and carefully designed programming method remove disturbance issues, and improve retention time more than 2 times or allow program/erase cycle more than 10 times. Our on-chip high voltage circuits are built using standard I/O devices but operates without any voltage overdrive by employing multi-stacking and multi-stage cascading techniques in high voltage switch and on-chip charge pump circuits. Thus, the designed high voltage circuit has no reliability concern while providing high enough program/erase voltage levels for cell operation and increasing the program/erase performance more than 10 times. Thus, we believe our customers will be able to make competitive SoC design with our cost effective, secure, reliable embedded flash memory IP.Single Poly Embedded Flash,Logic Compatible Embedded NVM,On-Chip NVM,Security IP,Energy efficient SoC,Cost effective SoC,Over-stress free logic compatible high voltage generator,Over-stress free logic compatible high voltage switch

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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