Adiabatic logic-based energy-conserving circuits have potential to significantly improve energy efficiency. Adiabatic circuits recycle charge stored in load capacitance resulting in lower power dissipation as compared to conventional CMOS. However, these circuits have only targeted low-frequency operations. Research is needed to develop adiabatic logic circuits for high performance applications without sacrificing the energy efficiency. Hence, the goal of this STTR proposal is to investigate and develop circuit design techniques that can enable adiabatic logic technology to work energy efficiently at high frequency. Phase I objectives include: (i) to design representative functional blocks used in logic and memory circuits using a range of conventional and adiabatic design techniques and implement them in a CMOS process, (ii) to design adiabatic logic based energy efficient multiplier-accumulator (MAC) as the benchmark circuit using the computing and memory units proposed in objective (i). Several benchmarking experiments will be performed to understand the tradeoffs between area, speed and energy efficiency of adiabatic logic circuits compared to standard CMOS. The proposed research will enable the Air Force to determine feasibility of adiabatic logic techniques to design high performing commercial processor technologies for ultra-low power, high performance, digital processing for space applications.
