SBIR-STTR Award

This effort will evaluate radiation hardened cache memory architectures with respect to future device parameter requirements; identify potential Air Force PNT systems, DoD, and commercial aerospace application requirements; select a suitable RH cache architecture to meet anticipated memory size, performance, and radiation requirements; and initiate the design of an advanced RH cache which meets or exceeds the noted radiation hardness levels. Cache memory has been used effectively for years to improve the computation performance of microprocessors. In microprocessors, the processor operations are performed on data contained within the register file via instructions that are loaded from main memory. Cache was implemented as a smaller, faster bridge between the register file and main memory to complement the processor speed. Systems operating in either a natural space or a nuclear weapons system radiation environment need radiation-hardened cache memory to ensure accurate processor functions. Scientic and Sandia National Labs (SNL) propose to leverage the efforts performed by our team in developing SONOS-based NVMs to identify, characterize, and design an advanced state-of-the-art RH cache architecture, tailored to the AF Space application requirements, which can be implemented in existing fabrication processes to reach this goal. Our concept is to build the basic RH cache out of commercially available static random access memory (SRAM) that meets the radiation hardness criteria except for single event upset (SEU), and mitigate the SEUs through the architecture. This will deliver the best cache performance with the least penalty from the radiation hardening.

Benefit:
Systems operating in either a natural space or a nuclear weapons system radiation environment needs radiation-hardened cache memory to ensure accurate processor functions. Potential applications for this device include command and control, navigation, communication, and data processing for interceptors, defense and commercial satellites, and other military and space flight systems. Successful completion of this program will result in a fully qualified, commercially available power efficient, high speed, radiation hardened cache memory device to meet system requirements. Commercialization of this device will involve a proven team consisting of Scientic, SNL, OSU, and NGC (where appropriate). Our team has been successful in developing, fabricating, qualifying, marketing, and selling 64Kb, 256Kb and 1Mb radiation-hardened SONOS-based EEPROM devices for defense and aerospace applications, and is currently developing a 128Mb radiation-hardened SONOS-based EEPROM under a SBIR Phase II contract to the Missile Defense Agency (MDA). Based on our past program history and device development successes, we anticipate supplemental funding to be available to support Phase III efforts. To ensure commercialization success of this program, the architecture and memory design selected in this Phase I effort will be compatible with a typical CMOS fabrication process flow to the greatest extent possible. As noted in Section 1.0, we will assess the SRAM fabrication options available at various trusted commercial processes. However, it is expected that one of the IBM silicon-on-insulator (SOI) processes will be the best suited for this project.

Keywords:
radiation hardened

Cache memory has been used effectively for years to improve the computation performance of microprocessors. In microprocessors, the processor operations are performed on data contained within the register file via instructions that are loaded from main memory. Cache was implemented as a smaller, faster bridge between the register file and main memory to complement the processor speed. Systems operating in either a natural space or a nuclear weapons system radiation environment need radiation-hardened cache memory to ensure accurate processor functions. Our goal is to develop and commercialize a power efficient, high speed, radiation hardened cache memory device suitable for long-term space missions using existing trusted commercial processes and IP combined with innovative design architectures. To accomplish this, Scientic and Sandia National Labs (SNL) propose to leverage the memory architectures, cell designs, fabrication processes, and hardening techniques identified during Phase I of this program to develop an advanced SOA RH cache memory device, tailored to the AF Space application requirements, which can be implemented in existing fabrication processes to reach this goal.

Benefits:
High reliability integrated circuits operating in either a natural space or a nuclear weapon system radiation environment requires radiation-hardened cache memory to ensure accurate processor functions. Potential military and/or DoD applications for this device include command and control, navigation, communication, and data processing for interceptors, defense satellites, and other military and space flight systems. Other high reliability markets include commercial satellites, aircraft electronics, automobile electronics, and medical electronics. The electronic devices created for these markets typically have to mitigate soft errors; it is definitely the case for aircraft and medical electronics. Our approach is fairly efficient in a speed/density/power sense and provides an extremely low soft error rate, likely better than that which is currently in use. For military and/or DoD applications, our approach will begin by marketing to those organizations to which Scientic, Inc. and SNL have an existing business relationship and rich heritage of successful program deliveries. These include AFRL, SMC, Naval Research Laboratory, MDA, USASMDC, and other Government agencies, all of whom have an interest in survivable control systems. We also have excellent relationships with commercial sector organizations (technology corporations/prime system developers) that are potential users and will market these organizations as well. These include Boeing, Raytheon, Lockheed-Martin, Northrop Grumman, Honeywell, BAE Systems, and others. Finally, as mentioned above we will leverage our participation in conferences, seminars, and symposia such as HEART, GOMAC, RHET, and others to introduce the RH MST to the broader user community. The civil market requires a broader approach. Unfortunately, the proposed development lacks significant commercial potential. Most commodity microprocessors are at the 32 nm or beyond and employ multiple levels of cache already. The RH cache concept proposed herein will not perform better than what they already use. However, there exist certain high-reliability markets where hardened cache memory would be beneficial. These include commercial aerospace, commercial aircraft electronics, automobile electronics, and medical electronics. Electronic devices created for these markets typically have to mitigate soft errors; it is definitely the case for aircraft and medical electronics. Our approach is fairly efficient in a speed/density/power sense and provides an extremely low soft error rate, likely better than what is currently in use. Another potential high reliability market is computer servers. Servers that maintain large commercial websites are intended to be highly reliable, but also have high capacity. It is possible that the approach proposed here would be an improvement over what these systems currently use. These areas of interest potentially offer a fairly large commercial market. Although the main potential of the RH cache is as a companion integrated circuit for RH microprocessors or microcontrollers, where extremely low bit upset rates are required, this RH cache would be more effective if embedded in the microprocessor or microcontroller. In addition, once the proposed RH cache architecture is validated, the architecture is portable to other fabrication processes. Therefore, another potential opportunity consists of selling the architecture concept developed under this program to RH microprocessor or microcontroller developers for inclusion in their product. Successful completion of this program will result in a fully qualified, commercially available power efficient, high speed, radiation hardened cache memory device and/or RH cache memory IP to meet system requirements.

Keywords:
radiation hardened, cache memory, survivability, total dose, SEU, L2, SRAM, single event upset