The proposed project will develop an ultra-wideband digital modem capable of processing a minimum 2.5 GHz occupied bandwidth, with an objective goal of achieving 5 GHz occupied bandwidth. The development will include the design and development of all associated signal processing algorithms, along with implementation of HDL code on an FPGA-based target platform. The modem implementation is intended to serve as the basis of a future SATCOM system exploiting V/W-Band spectrum. The development will culminate with the benchtop demonstration of the ultra-wideband modem operating in digital loopback on the targeted FPGA-based platform, including digital channel emulation impairments to aid in characterizing modem performance.
Benefits: Successful Phase II will result in a wideband, power-efficient modem implemented on low-cost commercial FPGAs operating at wider bandwidths and higher data rates in excess of what is available in the commercial, terrestrial market. Likewise, the FPGA implementation will provide a cost and price advantage compared to ASICs for the spaceborne equipment market.
Keywords: QPSK, modem, wideband, power-efficient, high-rate, FPGA