SBIR-STTR Award

An innovative approach to integrate high-level Digital-Signal-Processing (DSP) functions into the traditional Application-Specific-Integrated-Circuit (ASIC) development methodology for sub-micron radiation-hardened CMOS circuitry is proposed. The solution involves developing a high-level DSP block functions whose parameters are specified by the designer that will synthesize into high-performance lower gate count Radiaton-Hardened-By-Design (RHBD) structures. These high-level blocks will generate HDL simulation models and verification testbench models and can be re-used within the circuit or in other designs thereby reducing development schedule and verification risks.

Benefit:
This research will beneficially impact the development cycle and quality of commonly used Digital Signal Processing (DSP) functions. The methodologies used are directly and easily transferable from ASIC to ASIC as well as to other functions besides DSP. Benefits include rapid development time, substantial risk reduction and decrease cost and schedule. Potential commercial applications include common DSP applications such as communications, waveform digital processing such as demodulation, filtering and encoding and ASICs incorporating these functions.

Keywords:
Asic, Dsp, Rhbd, Sub-Micron Cmos, Design Methodology, Verification Reuse, Ip Reuse, Satellite Communications