The goal of the Phase I SBIR effort is to characterize and specify the application of the relevant parts of the MARTE profile into a class and component library including resources, networks, busses and other constrained-use artifacts (e.g. Devices, data tables, system locks, etc) so that a complete set of required performance objectives can be characterized for the aggregate set of components as well as for each individual constituent component. This data can then be accessed and acted on by the appropriate RMA, Queuing Theory and discrete event simulation tools to assess worst-case completion performance, average and statistical throughput information, and appropriate degraded mode operations context as needed. The characterization of performance objectives and implementation constraints as integral properties of each architectural design element makes the extraction of the appropriate collection of properties and their analysis easy to automate and facilitates insertion of analysis results into the architecture characterization as well. This foundation of architecture characterization is inherently extensible, since new properties and classes can easily be added as additional analyses and characterizations are required. Also the addition of this richer definition of real-time components will facilitate the ability to better analyze more complex distributed real-time architectures.
Benefit: The commercial marketplace would see add-on component profiles available to UML design tools to use the new capabilities, along with drop in analysis tools to automate the analysis and assessment of architecture performance for systems designed using the new and augmented capabilities. Additional exposure to the new UML profiles and classes would be all that is necessary. Such future use applies not only to DoD embedded systems, but equally well to enterprise systems, automotive systems, financial management systems, aircraft, Telecom, manufacturing and control industries and FDA approved software products. As the software and the technology developed within this SBIR infuses into those marketplaces and cultures, performance assessment will become a co-equal part of the design effort and architecture process through the automation and computer capture of architecture performance information made available through the products of this SBIR.
Keywords: Marte Profile, Distributed Real-Time Modeling, Rate Monotonic Analysis, Deadline Monotonic Analysis, Uml, Integrated Modeling And Analysis, Eclipse Framework Integration, Netw
