The objective of this proposed effort is to develop a Passive Brick which would allow any combination of passives to be accessible to a Field Gate Programmable Array (FPGA). By tightly integrating a FPGA with an often large population of peripheral components into a miniaturized 3D structure, the development and fabrication timeframe of the overall system will be reduced by concealing the complexity of the FPGA from system designers. While there are a limited number of FPGA devices, there is a very large number of passives and passive combinations that support an FPGA working device. The Passive Brick would be a one time programmable passive device that couples directly to the limited number of FPGAs and providing a rapid turn around for fabrication. By eliminating the complexity of the hundreds or thousands of peripheral components from the system designer, reconfigurable devices will be deployed in DoD and military applications with a dramatic reduction in both time and effort.
Benefit: The Passive Brick will add significant value to what is already highly desired in the FPGA, flexibility, reduced time in fabrication and reduced cost for small lots. By integrating Field Programmable Gate Arrays on a thin, flexible substrate, several design, power, size, and performance benefits can be realized that will shorten design cycles and create new field-use possibilities for many commercial and military applications. The Passive Brick is specifically and initially focused on FPGA and therefore this is the target where the marriage between the reconfigurability of the device and the programmability of the passive brick is well-suited. The Passive Brick also has the potential to expand to other active devices, such as micro controllers, microprocessors, and micro-systems. All active devices require supporting passives and therefore, the flexibility of using this to rapidly fabricate devices has significant potential.
Keywords: Fgpa, Direct Print, Nanotechnology, Miniaturization
