SBIR-STTR Award

Field Programmable Gate Array Based Channelizer
Award last edited on: 10/24/2006

Sponsored Program
SBIR
Awarding Agency
DOD : AF
Total Award Amount
$849,745
Award Phase
2
Solicitation Topic Code
AF05-017
Principal Investigator
Aaron Tu

Company Information

LinQuest Corporation

5140 West Goldleaf Circle Suite 400
Los Angeles, CA 90056
   (323) 924-1600
   N/A
   www.linquest.com
Location: Single
Congr. District: 37
County: Los Angeles

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2005
Phase I Amount
$99,954
Transformational Communications require the development of a reconfigurable low power radiation hardened channelizer capable of scaling up to support 25 20 MHz narrowband and wideband channels. Field Programmable Gate Array (FPGA) technology is ideal for rapid development of customizable circuit. Xilinx and Actel are the only vendors with radiation hardened FPGA having over a million usable gates count. Xilinx FPGA is based on SRAM technology which requires Triple Modular Redundancy (TMR) to eliminate Single Event Upset (SEU) while Actel FPGA is based on anti-fuse technology with triplicated gates. LinQuest is proposing to use Xilinx QPRO-R FPGA to satisfy Transformational Communications Channelizer requirement. This proposal will also review various channelizer architectures and implementations approaches. The final architecture will be simulated in C/C++, MatLab, and Verilog/VHDL. The channelizer design will be synthesized and routed for the purpose of accessing resource utilization, power consumption, and maximum clock speed. The final analysis will be Phase I deliverable. LinQuest is an employee-owned small business with exceptionally strong qualifications in the Military & Commercial Satellite Communication Systems, Engineering and Technical Assistance (SETA) arena. LinQuest has over 20 years of experience development state-of-the-art end-to-end simulation platforms (MEESE) providing SETA support for Milstar, AEHF, and now Transformational Communications (TSAT). Over the years, LinQuest has developed a library of channelization capabilities including channel coding, modulation, fading, jamming, and nuller functionalities. LinQuest’s engineers hold advance degrees and have extensive experience in flight hardware design including AEHF transponder and channelizer. Thus, LinQuest is uniquely qualified to support the development of Transformation Communications Channelizer.

Benefits:
LinQuest is still investigating potential commercial applications, however, the first application involves with significant potential involves the Transformational Communications (TSAT) payloads and terminals. LinQuest will work with TSAT JPO, payload, and terminal prime and subcontractors to incorporate the Channel Coding device as a result of this SBIR. In addition to these applications, LinQuest will study and identify appropriate commercial opportunities. LinQuest’s research and development in Turbo Code dated back to 1997. We believe our experience will allow us to take on any Turbo Code simulation, analysis, and development in area 3rd and 4th generation cellular and MUOS. Well recognized for our contribution and leadership among our client agency within the Department of Defense in programs such as MUOS, TSAT, AEHF, and Milstar. LinQuest has the personnel and system expertise to develop a state-of-the-art radiation-hardened channelizer.

Keywords:
channelizer, channelization, TSAT, radiation hardened, transformational communications, FPGA, turbo

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
2006
Phase II Amount
$749,791
Our proposed radiation hardened FPGA based turbo codec development has two primary objectives critical to reducing risk on the Transformational Communication Satellite (TSAT) program. The first objective is to develop an innovative highly efficient turbo codec core solution that supports TSAT. TSAT requires significant improvement in the waveform processing capability to meet increased throughput requirements as well as dynamic changes in data rates. The turbo codec core solution is critical as it must overcome space, weight and power (SWaP) constraints that limit the number of FPGAs while overcoming the FPGA’s relatively slow clock speed limitation. The second objective is the development of a prototype board with target FPGA’s and associated test bed designed to meet the radiation hardening requirements in addition to the performance requirements. Both of these objectives are aimed at reducing the risk associated with FPGA/ASIC selection which has resulted in cost and schedule impacts to the AEHF program

Keywords:
TSAT, Radiation Hardened FPGA, Turbo Codec, On-Board Processing, SWaP, Risk Mitigation, High Throughput, Slow Clock Speed