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SBIR-STTR Award
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SBIR-STTR Award
10
Latch-Up Detection and Cancellation in CMOS VLSI Circuits
Award last edited on: 4/3/02
Sponsored Program
SBIR
Awarding Agency
DOD : AF
Total Award Amount
$82,400
Award Phase
1
Solicitation Topic Code
AF99-030
Principal Investigator
Philippe O Pouliquen
Company Information
Padgett-Martin Technology
4222 Falls Road
Baltimore, MD 21211
(410) 516-0257
N/A
N/A
Location:
Single
Congr. District:
03
County:
Baltimore City
Phase I
Contract Number:
F29601-99-C-0069
Start Date:
4/27/99
Completed:
4/10/00
Phase I year
1999
Phase I Amount
$82,400
Latch-up in a large digital system can be isolated to a small portion of the total die area. In success cases, the increase in current drawn from the supply is not distinguishable from the much larger average current consumed by normal operation. This makes it difficult to detect micro-latch-up by observing the current consumption of the entire chip. We propose a technique which senses the voltage differences across the source to bulk junction of the transistor. This signal in turn is used to control a local switch to the power supply of the effected circuits. When a micro-latch-up condition is detected the affected block of logic will be power cycled to alleviate the latch-up condition
Phase II
Contract Number:
----------
Start Date:
00/00/00
Completed:
00/00/00
Phase II year
----
Phase II Amount
----
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