SBIR-STTR Award

Advanced Embedded Test Processor
Award last edited on: 4/2/02

Sponsored Program
SBIR
Awarding Agency
DOD : AF
Total Award Amount
$96,530
Award Phase
1
Solicitation Topic Code
AF99-055
Principal Investigator
Maria Tirabassi

Company Information

JTA Research Inc

3010 Old Ranch Parkway Suite 300
Seal Beach, CA 90740
   (562) 795-9153
   N/A
   www.jta.com
Location: Single
Congr. District: 48
County: Orange

Phase I

Contract Number: F29601-99-C-0089
Start Date: 4/30/99    Completed: 4/10/00
Phase I year
1999
Phase I Amount
$96,530
Today's complex DoD and commercial satellite systems require a sophisticated test and fault monitoring approach for enhanced telemetry. Hence, an embedded test processor capable of monitoring faults in real-time and relaying the information to the satellite's control processor is needed. In addition, a smart processor capable of performing built-in test upon command would provide critical information necessary to isolate faulty units or circuitry within the spacecraft. This same technology is required in high-end consumer commercial hardware during manufacturing and in-field test. The convergence to systems-on-chip accelerates the need for a "smart" embedded processor capable of providing test access to complex blocks of logic now embedded within a single ASIC. The Advanced Embedded Test Processor satisfies the DoD, commercial satellite, and consumer market need for a programmable, real-time fault monitoring and built-in-test controller targeted for implementation in VHDL

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
----
Phase II Amount
----