System Excelerator Inc. (SEI) proposes to develop a 3-axis high G accelerometer subsystem capable of greatly improved high G performance range and accuracy (>>5000 G's) packaged in a cube sized smaller than 0.5" by 0.5" square and able to survive and operate in high shock environments. This subsystem will use the first prototype versions of a novel single chip MEMS high G accelerometer, the AD181, by Analog Devices (ADI). The AD181 containing both a high G micromachined sensor and integrated signal processing components on one device has been deigned for fuzing applications. This device was sponsored under the ARPA TRP primed by ADI. The main goal of the proposed Phase I effort will be to demonstrate the ability that a small package containing three AD181 devices will sense high G acceleration in an ultra high G environment. Three of these AD181 devices will replace the first generation ADXL50 MEMS accelerometers currently packaged into a small .5" cube for this demonstration. The existing DSP MEMS tester board developed under the TRP contract will be modified to accept all three AD181 analog self test ports simultaneously to test a variety of 3-axis test conditions. Additionally, the existing ADI Matlab XL181 simulation model will be upgraded to describe the 3-axis accelerometer, internal processor elements of each chip, and the external DSP functions required to process the 3 simultaneous accelerometer devices operating in harsh G environments. Both simulated deceleration signatures and real data will exercise this model. During the project, the present device sensor design will be adjusted for a high maximum range of acceleration and the design will be simulated to prepare for refabrication. Selected deceleration signatures will be analyzed via Wavelet techniques used originally for speech signature characterization to `tune' the MEMS sensor and internal processing functions to respond optimally to critical military target signatures. An optional set of tasks would allow for the quick `breadboarding' of the triaxail module and the interface processor breadboard that would facilitate Phase II redesign efforts to development devices capable of processing up to 10,000 G during deceleration.
