We propose to develop a what-if analysis tool for hardware/software co-design. It will provide a test-bed in which the user can quickly evaluate hardware/software co-design trade-offs. No tool currently available in the ESDA market supports this essential step in hardware/software co-design. Several new trends have made the current system design practice of separately developing hardware and software components increasingly untenable. The demand for new technology products involving video ,audio, and communication applications and the increasing prevalence of "algorithm on a chip" strategies indicates that the hardware/software divide is in a state of flux, and good system design must ensure that hardware/software trade-offs are investigated as part of the design process. However, this requires efficient tool support. Our proposed tool will provide the enabling technology to carry out this essential step in hardware/software co-design. The central feature of the tool is quick and automated development of a VHDL performance prototype of both the software and hardware components of the system. The software elements of the system are represented as a VHDL testbench, the hardware elements as VHDL performance models, and the integrating software and hardware elements as a single VHDL entity. During Phase I we will develop the architecture of the tool and test out the methodology with a hardware/software co-design example. We will be assisted in this work by Motorola's Chicago Systems Research Laboratories. The goal of Phase 2 is to implement, integrate, and productize the tool.
Keywords: Hardware-Software Co-Design Hardware-Software Co-Design Partitioning Partitioning
