Eleven separate efforts will broadly address four areas: (1) The development and verification of models for the temperature rise with power dissipation in high electron mobility (HEMTs) and heterojunction bipolar (HBTs) transistors, and the integration of the models into a device simulator, (2) The optimization of HBT layouts and layer structures to minimize temperature rise and base-collector capacitance and to maximize performance, (3) Tying out different HEMT layer structures and layouts to investigate such factors as the use of double channels in pHEMTs, spacer layer effects on HEMT noise figures, donor thickness effects on device performance and the source and drain resistances, and the effects of using very long fingers on high frequency performance, and (4) Enhancing Gateway Modeling's G-PISCES-2B Poisson and current-continuity equation solver and POSES Poisson-Schroedinger equation solver to include velocity overshoot, to simulate radial-symmetric HBTs under base-current drive, and to simulate double-channel pHEMTs.
Keywords: Hemt Hemt Hbt Hbt Field Effect Transistor Field Effect Transistor Thermal Impedance
