SBIR-STTR Award

The ability to manufacture large multichip modules with reasonable yields and costs is hindered primarily by the problem of burn-in losses, which can be as high as 5% per chip. One solution would be to perform a "burn'in" of the bare chips (dice) prior to their assembly into a multichip module. No proven manufacturing processes exist yet to do this. It is the ultimate objective of this project to develop such a capability. Our general approach is to use a relatively low-cost high-density interconnection substrate such as a "silicon circuit board" or a flex-circuit to distribute power, clock, and data levels to an array of die mounting sites on its surface. Each die would be positioned with its i/o bond pads facing the interconnection substrate, with means for temporarily electrically connecting these bond pads to the substrate for the duration of the burn-in. The phase i effort will focus on evaluating the feasibility (both analytically and experimentally) of various proposed inter- connection methods, with emphasis on reliable attachment and detachment to aluminum bond pad metallurgies, while avoiding any damage or contamination to the die and its bond pads.

The primary objective of this proposal is to develop and demonstrate a manufacturable process for wafer-scale burn-in of state-of-the-art semiconductor device wafers. The potential technical feasibility of two such techniques was explored in a previous Phase I contract, with positive results. One such approach has been selected as the preferred approach for this Ph II effort. The technique uses a bumped, high-density interconnect "silicon circuit board" to mate face-to-face with the device wafer, providing a functional replacement for the traditional burn-in board. The technical effort is centered on characterizing the quality of the electrical connection, optimizing the burn-in substrate for maximum reusability, and developing the electrical, mechanical, and thermal techniques needed to make the wafer-scale burn-in concept feasible and demonstrable. Two different types of functional device wafers will be configured and tested using the techniques developed herein. The results will be analyzed to determine whether wafer-scale burn-in is in fact an effective substitute for conventional (packaged IC) burn-in.