SBIR-STTR Award

This R&D project is directed toward the identification of SOI/SIMOX circuit hardening techniques for reentry system linear electronics. critical generic linear circuit functions will be selected following a review of present reentry system linear requirements. selected circuits will be designed using CMOS/SOI electrical and layout ground rules. Preliminary layouts will be performed to identify geometric parameters. Computer simulations of circuit response to permanent radiation effects and prompt and wide pulse ionization will be performed, hardness levels predicted and circuit hardening techniques evaluated. The proposed approach will result in extreme neutron damage and SEU and ionizing radiation upset tolerance. Total dose hardness will be addressed by design while taking advantage of the recent technology hardness improvements.