Fail safe fault-tolerant electronics
Award last edited on: 9/5/2002

Sponsored Program
Awarding Agency
Total Award Amount
Award Phase
Solicitation Topic Code

Principal Investigator
Janis Pukite

Company Information


4960 Fillmore Street NE
Columbia Heights, MN 55421
   (763) 572-0998
Location: Single
Congr. District: 05
County: Anoka

Phase I

Contract Number: N/A
Start Date: 00/00/00    Completed: 00/00/00
Phase I year
Phase I Amount
Future military avionics systems will require at least an order of magnitude improvement in mean time between critical failures. To achieve this goal innovative fail-safe fault-tolerant electronic system design concepts will be needed. The approach proposed by daina will be based on the use of external environment data, built-in reliability model, adaptive statistical system state and parameter estimators, software hooks, signal fusion, and application of artificial intelligence techniques. It is expected that by maximizing the utilization of the available information more reliable fault detection and isolation will beachieved, reliability improved, and false alarm rate decreased, allowing the aircraft to continue mission even after experiencing hardware or software failures or combat damage. Improvement in fault-tolerant system design aids will be recommended to support reliability and safety evaluation of the proposed designs. Phase i of this effort will include an assessment of avionics system requirements, identification of high-payoff hardware and software technologies, evaluation of redundancy and reconfiguration implementation, and determination of computer-aided design support tool needs. Phase ii will involve a prototype development of the selected fail-safe fault-tolerant electronics and the supporting technology needs.

Phase II

Contract Number: N/A
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
Phase II Amount
Future Avionics Systems will require capabilities in computing power, performance, and reliability that are not currently available. The Phase I effort identified Wafer Scale Integration (WSI) as a leading candidate for these applications. However, the methods and models for reliability, yield and plan redundancy for WSI circuits are inadequate. Similarly, the models for reliability, thermal and stress analysis are not refined for WSI. New WSI design methods and tools will be needed to support the design of the next-generation fault-tolerant avionics architectures. The proposed WSI simulator will aid in yield prediction and redundancy planning and will evaluate various parameters that affect wafer scale architecture, performance, reliability, availability, and cost. The critical parameters include signal delays, wafer yield, defect tolerance, dynamic fault-tolerance, heat removal capability, and mechanical integrity. Since the importance of these effects is magnified for WSI circuits, new techniques will be developed to estimate their impact for various WSI configurations and to select the optimum configuration. A tradeoff program will be developed to optimize these parameters and thereby to improve wafer yield. Dynamic fault-tolerance simulation capability will also be provided to estimate the effect of operational faults and to predict the reliability of WSI