SBIR-STTR Award

Micromachining gaas wafers hold promise of flatter wafers, with better parallelism (uniformity of thickness), which in turn promises better yield and circuitry repeatability. Moreover, the same process can be used to provide better control of post-circuitry thinning. Experiments will be conducted to improve surface finish and reduce subsurface damage. Handling and chucking techniques will be developed to reduce handling hazards after thinning.

The Phase I effort result in micromachined gaAs wafers with 200 angstrom peak-to-valley surface finish, positive electrical characteristics, and one micrometre or less depth of crystal damage. A state-of-the-art planar cutting machine will improve these results. Functional performance comparing simple FET circuitry on micromachined and conventional wafers will indicate possible yield improvement. A 0.5 micrometre depth of cut indicates promising material removal control during backside thinning without threatening flatness and parallelism.