Rapid technological developments in missile function and defense weapons advance require the implementation of radiation hardened, high performance missile computers which meet significant size and weight constraints. In order for U.S. missile technology to meet increasing future threats, missile computers must be implemented with radiation hardened VHSIC technology. Different computer architectures such as reduced instruction set (RISC), pipelining, and parallelism need to by: investigated and optimized to VHSIC device implementation yet achieving high performance. Based on architecture and technology issues, VHSIC devices will be partitioned to achieve minimum device count and achieve radiation hardness.
