SBIR-STTR Award

This Small Business Innovation Research (SBIR) Phase I project addresses decreasing the Spin Transfer Switching (STS) critical current through the innovative application of magnetic materials. STS allows for the manipulation of the magnetic order parameter of nano-scale ferromagnets without the use of external magnetic fields and is recognized as a key component for scalability of magnetic random access memory (MRAM). One of the major technical barriers to realize practical spin dependent electronic devices based on STS is the large current needed for switching. One approach to reduce the STS critical current is to magnetically engineer ferromagnets to have precisely the characteristics needed to enable switching. This critical current has been reduced to 10^6 A/cm2, however, a further order of magnitude reduction is needed. Magnetically engineering the out-of-plane anisotropy of thin sub-micron ferromagnetic through further innovative materials research could lead to this reduction. Control of the magnetic anisotropy through innovative materials research has been studied but applying these to practical devices has not. Reduction of the STS critical current is vital to the enabling a spin-dependant electronic devices for storage, logic, and oscillator devices. These solid-state devices have the potential to drive improvements in electronics, and create an entire new sector of the semiconductor industry.

This Small Business Innovation Research (SBIR) Phase II project will address the critical steps needed to manufacture a fast, non-volatile, magnetic random access memory (MRAM) based on spin transfer torque (STT-RAM). STT-RAM which uses spin polarized current to switch individual bits is predicted to have better scaling properties than conventional MRAM which uses magnetic fields. This Phase II project will focus on sub-100nm device manufacturability, device performance testing, and circuit design to develop a set of results which will enable the creation of a 1 Mb demonstration chip. The STT-RAM test chip is needed to prove the technology for customers. The results obtained from this project will include the development of arrays of sub-100nm bits, with the appropriate thermal stability, read/write characteristics and distributions. Also addressed will be the reliability of reading and writing such small devices. The project will develop processes for manufacturing sub-100nm structures. Finally, a simulation of read and write circuitry based on STT-RAM will be produced allowing for tape-out of a 1 Mb test chip. Commercially, as microelectronics scales to smaller sizes and higher speeds, more features are added to typical consumer electronic devices and the demands on memory continues to grow. These demands and the inherent limitations of existing technologies create opportunities for new memory technologies to fill. As a leading candidate for a future universal memory that incorporates all the desired characteristics; non-volatility, high speed, low power, unlimited rewriting capability, extendibility to future semiconductor nodes; STT-RAM is in a strong position to take advantage of these opportunities