SBIR-STTR Award

This Small Business Technology Transfer Phase I research project will demonstrate a globally asynchronous, locally synchronous (GALS) methodology for the design of large-scale, deep-submicron, System-on-Chip (SoC) integrated circuits fabricated in Field-Programmable Gate Arrays (FPGAs). The methodology utilizes a Delay-Insensitive (DI) interconnect between conventionally clocked subsystems. The interconnect components are bundled data paths and a set of control elements whose designs are DI and hazard-free across processes and submicron scaling. These control elements are defined by Petri net models or their trace theory equivalents. Prototype software has been developed to synthesize, from their defining models, the required logic for these elements. Hazards are identified, logic hazards eliminated and metastability hazards managed. The methodology, in contrast to other approaches, allows the synthesis of a variety of arbiters from their models and includes novel stability detectors that can be implemented in FPGAs. The proposed work will improve the reliability, breadth and ease-of-use of the synthesis software and demonstrate a significant multiprocessor FPGA architecture. The proposed integrated circuit design methodology can substantially decrease the difficulty of designing billion-transistor, integrated-circuits for the SoCs of the future. The proposed GALS methodology will be introduced in the increasingly popular FPGA sector where other clockless designs have failed to leave the research laboratories. The proposed methodology has the potential to markedly decrease design cost and time-to-market of the large, specialized systems of the future

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5). This Small Business Technology Transfer (STTR) Phase II research project will develop and apply a principled design methodology to confront the serious problems associated with deep sub-micron, system-on-chip, integrated-circuit designs. The project will develop design services for companies wishing to market complex, proprietary, low-power integrated circuits through the development of a unique design tool, one which will apply a mathematically sound approach to the production of large, hazard-free, network-on-chip products. The goal for this tool is to reduce traditional design cycles by eliminating most of the global verification effort while improving the robustness of the design. New results in predicting the behavior of deep submicron arbiter circuits are essential to this work and will also be reported. The broader impacts of this research are to reduce design costs, time-to-market and power consumption. More broadly this can: 1) significantly increase the productivity of integrated-circuit design engineers, 2) reduce power consumption of electronic control, communication and computational systems and 3) increase our competitiveness against off-shore system-on-chip designers particularly with respect to low volume products. Thus, successful completion of this project is important to the future of the national electronics marketplace because, without a major reduction in the time spent on global verification, the benefits of higher levels of integration, including reductions in time-to-market, conservation of power and increases in reliability, will not be available to many important electronics market sectors