Moving into the 21st century, applications in information technology, biomedical, communication, and military capabilities are enabled by the availability of still higher semiconductor device complexity and speed. New thin film deposition processes are essential for the pursuance of the development of advanced memory cells and CMOS gate insulators. The SIA International Technology Roadmap for Semiconductor (ITRS) has alerted the development community of these needs. This program proposes to demonstrate the engineering of parasitic interfacial dielectrics (EPID) for advanced capacitors and the composition of interfacial dielectrics for gates, which are limiting factors. The Phase 1 of this program evaluates a proof-of-concept to a novel approach that enables a critical capability for engineering interfaces for integrated dielectrics. System tooling that has high reliability and good maintainability features are already partially developed and contemplated for use at the outset of this program. The deposition method uses an adaptation of Atomic Layer Deposition (ALD), which enables processes for controlling the interface properties of the dielectric at the atomic level. This effort is targeted to meet the needs for the 100-30 nm generations for uniform and conformal deposition. Anticipated Benefits/Commercial Applications: The benefits are to allow better performance and utilization of the use of high K dielectrics on semiconductor (silicon) electrodes. The ultra-thin film layers developed will play a role in the increased capacitor density of DRAM and other on-chip capacitors and increased speed performance of advanced high k dielectric gates.
Keywords: Atomic Layer Deposition, Dielectrics, High-K Dielectrics , Semiconductor, Ultra-Thin Film, ALD, Dielectric Interfaces
