SBIR-STTR Award

Epitaxial Liftoff for Low Power Reduced Parasitics Multi-Chip Modules
Award last edited on: 10/13/2005

Sponsored Program
SBIR
Awarding Agency
DOD : AF
Total Award Amount
$839,775
Award Phase
2
Solicitation Topic Code
AF98-092
Principal Investigator
Mike Sickmiller

Company Information

Elo Technologies Inc

2443 208th Street Unit E4
Torrance, CA 90501
   (310) 782-6850
   N/A
   www.elotechnologies.com
Location: Single
Congr. District: 43
County: Los Angeles

Phase I

Contract Number: F29601-98-C-0086
Start Date: 4/22/1998    Completed: 4/10/1999
Phase I year
1998
Phase I Amount
$100,000
The objective of this effort is to develop ultra-low power semiconductor packaging techniques for Multi-Chip Modules. Substrate parasitics contribute to excess power consumption of semiconductor devices. Through substrate removal techniques, capacitance can be lowered and operating power can be significantly reduced. By thinning the semiconductor chip to the thickness of the device only, with no substrate, we can both eliminate stray substrate parasitics and reduce interconnect parasitics therefore reducing total power consumption.As semiconductor device frequencies climb, so, proportionally, does substrate parasitic power consumption. Through ELO, parasitics to the semiconductor substrate are completely eliminated. As an added benefit, the devices can be mounted directly to the heat sink without the thermally insulting substrate impeding heat sinking. Through epitaxial liftoff for MCMs, we can reduce semiconductor power consumption, reduce package interconnect power consumption, and improve heat sink efficiency all at the same time.

Phase II

Contract Number: F29601-99-C-0022
Start Date: 5/28/1999    Completed: 8/28/2001
Phase II year
1999
Phase II Amount
$739,775
The objective of this effort is to develop high density semiconductor packaging techniques for dense, high power, Multi-Chip Modules. By thinning the semiconductor chip to the thickness of the device only, with no substrate, we can eliminate long thermal paths while minimizing interconnect parasitics. As semiconductor device frequencies and circuit densities climb, so, proportionally, does power consumption. The devices can be mounted directly to the heat sink without the thermally insulting substrate impeding heat sinking. The ELO Packaging Process will improve electrical and thermal performance, increase circuit and package density, and increase system integration while reducing the size, weight, and cost of the package and system. We have proven the fundamental manufacturing technology in the first half of the ongoing Phase I effort using actual production power amplifier chips. We have identified both existing and future applications for immediate and sustained market acceptance of this technology.

Benefits:
Improved electrical and thermal performance, increased circuit and package density, and increased system integration with reduced size, weight, and cost of portable electronic and wireless communications systems.