As neural networks are scaled up in size and complexity, network communication becomes more and more a central issue in system architecture. This is especially true for neuromorphic analog VLSI implementation that seek to mimic detailed biology in real time and in very high speed digital implementations. There is need for a communication architecture that has sufficient bandwidth and which preserves timing and causal order of events being represented such as action potentials. The architecture should be designed for easy adaptation to a variety of communication channels and bus standards, and it should be interoperable with a variety of existing local and wide area networking standards. The Neural Internet Project seeks to address these issues in order to help create the infrastructure necessary to support small systems being built today and very large systems expected to emerge in coming years. This project extends system integration technology already developed in the Silicon Cortex Project supporting analog VLSI neural network systems. This is done by developing a protocol for neural event messages that can support large address spaces of neurons and synapses and a prototype of a router to selectively filter, transform, monitor, and route event messages between different domains of neural communication.
Keywords: Bus Network Router Neuromorphic Neuroscience Vlsi
