SBIR-STTR Award

Development of Thermal Spray Circuit Board (TSCB) Technology for Hybrid Circuits
Award last edited on: 3/28/2002

Sponsored Program
SBIR
Awarding Agency
DOD : DARPA
Total Award Amount
$74,114
Award Phase
1
Solicitation Topic Code
SB991-007
Principal Investigator
William J Lenling

Company Information

Thermal Spray Technologies Inc

515 Progress Way
Sun Prairie, WI 53590
   (608) 825-2772
   info@tstcoatings.com
   www.tstcoatings.com
Location: Multiple
Congr. District: 02
County: Dane

Phase I

Contract Number: DAAH0199CR127
Start Date: 4/6/1999    Completed: 12/31/1999
Phase I year
1999
Phase I Amount
$74,114
The multi-million dollar market of Hybrid electronics is thriving despite the problems with the current manufacturing technologies. Processes like direct-bond-copper and other manufacturing techniques used to create Hybrid circuits are very time consuming, expensive, and produce hazardous wastes. Thermal Spray Technologies (TST) proposes funding for the development of a novel thermal spray process for producing hybrid circuits. TST recently developed the capability to deposit circuit traces directly onto polymeric based substrates using a sophisticated technology they dubbed the Thermal Spray Circuit Boards (TSCBs) technology. TST also produces high-density ceramic coatings for electrical insulation in many of its current products. TST proposes to deposit its high-density dielectric ceramic material directly onto a heat sink and then using its proprietary TSCB technology deposit a circuit pattern directly on top of the ceramic. The successful development of a thermal spray process that would be able to fabricate hybrid circuits by depositing a ceramic layer on top of a heat sink succeeded by a TSCB on top of the dielectric would be tremendous in the amount of money and processing time saved. The new commercial and military applications would be vast due to the flexibility in circuitry design and cost savings that this novel technology would bring.

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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