This Phase I project has two primary objectives. The first objective is to evaluate the feasibility of a fully ion implanted fabrication process based on the heterodimensional 2-D MESFET. The new device, the 2-D JFET, will have p+ ion implanted sidegates which laterally modulate a thin, highly doped n-type conducting channel. The 2-D JFET should have excellent high speed, low power characteristics and be easily manufacturable. The second technical objective of this Phase I project is to develop fundamentally new heterodimensional miser and amplifier devices for advanced wireless communications applications. We propose to utilize the dual gate functionality of the 2-D MESFET to replace several components of a conventional receiver front end with a single device, thereby radically reducing power consumption and improving manufacturability. This new technology offers substantial reduction in the power consumption of high speed, high frequency analog and digital circuits having applications in dual-use electronics including wireless communications systems, portable computers, consumer and space electronics, security systems, and medical electronics.
Keywords: Low Power Electronics, Integrated Circuits, Wireless Communications, Digital Receivers, Microelectro
