SBIR-STTR Award

We propose to enhance a previously designed and built processor interconnection network to make a distributed multiprocessor system that both has higher performance and is substantially more fault tolerant. The philosophy is to provide a system with: rapid, reliable global detection of system status changes with negligible impact on the host processors; in particular, no host message processing during steady state operation. Standard PCI interfaces so heterogeneous processors are supported minimal impact on system performance, which means simple added logic, primarily in hardware, and small bandwidth penalty. Competitive price and performance with 1 Gb/s links, flexible levels of status monitoring and fault recovery. The techniques used are: geographically distributed, functionally-interchangeable processing elements that are richly and redundantly interconnected. Optical data links to extend component separation and link bandwidth, hardware detection of several failure scenarios, ranging from application software paralysis to power failure, resulting in rapid optical bypass of the affected component. Hardware monitoring with system global software notification only with status changes, so host processor cycles expended only if absolutely necessary. Parallel, transparent processing at each interconnect node of a special status packet to update local status and transmit global status.