New direct bonding techniques will be used to stack very thin (<25 mm) semiconductor circuits (silicon or GaAs) to obtain 3D multichip stacks of ultimate density and performance. Due to the extreme thinness of the layers, vertical electrical interconnections (vias) can be formed without limitation. The proposed 3D integration technique will offer the following advantages: low weight and volume, low power, high interconnection density, improved reliability and radiation hardness, and faster speed and compatibility with various device and packaging technologies. We will deliver in Phase I, a sample that demonstrates the combined technology of existing thinning, bonding and interconnecting techniques and a second sample that demonstrates a new, batch stacking and interconnecting technology. Successful conclusion of Phase I will result in technologies that can be employed to fabricate an application-specific prototype device defined by NASA/JPL with the above mentioned advantages in Phase II.
Potential Commercial Applications:Very thin layer stacking technology will be crucial to all NASA applications, e.g., advanced flight computer (AFC) or solid-state recorder, where minimization of weight, volume, and power are essential to the success of the missions such as micro spacecraft for deep space explorations. POTENTIAL COMMERCIAL APPLICATION include mass-memory for synthetic aperture radar, database machines, digital library, and real-time image processors for computer graphics.
