SBIR-STTR Award

Design-for-test (DFT) involves the generation of test structures, the modification of the design to incorporate the test structures, the generation of test data and the verification of both the test structures and the test data. DFT usually occurs within a standard design flow incorporating capture, synthesis, and simulation capabilities. Existing point solutions generate some structures such as scan-chain, 1149.1 elements and do not generate all the necessary structures. Existing point solutions require the designer to be intimately familiar with DFT and require that he/she understand both the structure and its connections with the rest of the design. Conventionally, it is the responsibility of the designer to both maintain and re-use test data/structure(s). LogicVision's existing solution provide the ability to generate built-in self-test (BIST) and various other structures at the RTL and higher up levels. LogicVision intends to develop a configuration manager which will maintain all the test structures/data generated by the tools and by operating at the RTL and higher levels, the structures are connected by the configuration manager with the rest of the design. The tools thus permit the re-use of test objects and test data across the hierarchy of the design. This will result in a vertically integrated hierarchical test automation solution, which will increase designer productivity and also improve the quality of the design.

This Phase II proposal presents a development plan for a Configuration Manager that further automates the hierarchical integration of Design for Test (DFT) capabilities into the MCM/PCB and IC levels. This Electronic Design Automation (EDA) tool is used in the normal design flow, in conjunction with DFT point tools automating BIST and 1149.1, to achieve a hierarchical specification and integration of DFT that supports integrated test and integrated diagnostic capabilities. The Configuration Manager serves as a unifying tool by capturing the hierarchical DFT specification as a test protocol hierarchy and using it to tie together all the BIST structures, 1149.1 test busses and test data, generated by the DFT point tools, with the rest of the design. It provides greater automation, increased ease of use and the possibility of re-use, all of which result in significant savings in time, effort, and expenditures in the development cycle. In addition, the Configuration Manager provides a graphical user interface based on X-windows/Motif and is intended to work stand-alone or within a broader Design Framework.