SBIR-STTR Award

A physical artifact for the improved accuracy of wafer level critical dimension measurements
Award last edited on: 12/30/2009

Sponsored Program
SBIR
Awarding Agency
DOC : NOAA
Total Award Amount
$50,000
Award Phase
1
Solicitation Topic Code
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Principal Investigator
J Jerry Prochazka

Company Information

VLSI Standards Inc

3087 North First Street
San Jose, CA 95134
   (408) 428-1800
   marc.heivey@vlsistd.com
   www.vlsistd.com
Location: Single
Congr. District: 17
County: Santa Clara

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
1995
Phase I Amount
$50,000
The National Technology Roadmap for Semiconductors presents guidelines for 0.25 um devices by 1998, with 0.18 umgeometries following in 2001. In order to meet this goal from a metrology standpoint, accurate and precise physical linewidth calibration artifacts must be developed. Currently, the onlycalibration artifacts commercially available are a O.g umreflected light standard (manufactured by VLSI Standards, quartzor wafer mounted) and a 0.5 um transmitted light Standard fromNIST (SRM 473).The intent of this phase 1 proposed study is to provide amethodology to manufacture and characterize linewidth standardsin the range of 0.40 to 0.35 Am, with extendibility to 0.18 um bythe end of the decade. A detailed feasibility analysis wouldoutline the characterization process which would be accomplishedby a two-pronged approach: I) under an already existing NISTCRADA (Cooperative Research and Development Agreement) betweenVLSI Standards and NIST, a Calibrated Atomic Force Microscope(C-AFM) would be employed for certification of the linewidth. 2)As an adjunct measurement tool, angle-resolved light scattering(ARLS) would be used to determine linewidth This method couldalso employ a "first principles" traceability path to NIST basedon the wavelength of the laser employed.Potential commercial application of the research:Sub O.5 umlinewidth standards are required for US semiconductormanufacturers to Main competitive according to the upcomingtechnology nodes of the National Technology Roadmap forSemiconductor;. Under this proposal, an enhanced research planbecomes viable to offer congenially available critical dimensionstandards to fill this cam void.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
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Phase II Amount
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