SBIR-STTR Award

The Least-Squares (1. s . ) algorithm is the basis for many modern signal processing applications including spectral analysis, beam formation, direction finding, adaptive antenna array, equalization, Kalman filtering and parameter estimation. Triangular and linear systolic arrays are the most efficient ways to achieve high computational throughput rates for high performance real-time applications.The researchers propose a detailed comparison of the arithmetical complexity (number of multiples, divides, etc.) and finite precision computational effects of the triangular and linear internal and boundary systolic processing cells under Givens, fast Givens, modified fast Givens, modified Gram-Schmidt, and Householder transformations for l.s. estimation based on the QR decomposition approach. By selecting the processing al-gorithm with the least computational complexity, they can determine the architecture of the high throughput rate systolic array processor for VLSI fabrication. A generic (programmable) systolic array pro-cessing chip can be developed for a variety of signal processing applications.Commercial Applications:Least-Squares signal processors have applications to guidance, radar, sonar, communications, image processing and robotic vision systems.

The least-squares (I.s.) algorithm is the basis for many modern signal processing applications including spectral analysis, beam formation, direction finding, adaptive antenna array, equalization, kalman filtering and parameter estimation. Triangular and linear systolic arrays are the most efficient ways to achieve high computational throughputrates for high performance real-time applications. The researchers propose a detailed comparison of the arithmetical complexity (number of multiples, divides, etc.)and finite precision computational effects of the triangularand linear internal and boundary systolic processing cells under givens, fast givens, modified fast givens, modified gram-schmidt, and householder transformations for I.s. estimation based on the qr decomposition approach. By selecting the processing algorithm with the least computational complexity, they can determine the architecture of the high throughput rate systolic array processor for vlsi fabrication. A generic (programmable) systolic array processing chip can be developed for a variety of signal processing applications.